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[000000e0] 48 00 49 00 4A 00 4B 00 4C 00 4D 00 4E 00 4F 00 H. MAC Address: : F:9C (Network Research) Nmap scan report for rfc1918.edu (192.168.2.57) Host is up (0.000093s latency).

MAC Address: : F:5C (Network Research) Nmap scan report for rfc1918.edu (192.168.2.56) Host is up (0.000087s latency).

Both cms2 and cmssun4 (and the other machines in CMS Lab) are connected to a D-Link switch which then connects to the outside world: FED: 0 Ev N: 0da000 Bc N: 224 Or N: 0002bcd2 TTS: 0/0 Ev Typ: 1 Cal Typ: 0 Size: 236 UHTR 1 [ 444] Ev N 0da000 Bc N 224 Or N 13 FED: 0 Ev N: 0dc000 Bc N: a78 Or N: 0002c1ac TTS: 0/0 Ev Typ: 1 Cal Typ: 0 Size: 236 UHTR 1 [ 444] Ev N 0dc000 Bc N a78 Or N 0d #39 is dead because most likely one of the components on the 12V line is shorted to ground so there's no power supply for the module. 011af0 06f306f206f106f0 06f706f606f506f4 011b00 06fb06fa06f906f8 705f06fe06fd06fc 011b10 0000000000000a00 a00003891aca0000 to set up L1A: set L1a to about 20KHz start ttc/trig 4(turn off L1A) run amc13tool wv 3 410 (enable amc5 and amc11) wv 1 1 (set run bit) wv 0 1 (reset all) ttc/cmd 0x28(reset orbit number) ttc/trig 1 (enable L1A) this will take 0x800 events in the memory and throw away all when the buffer is full.

Connectivity to each other and to the outside world was spotty. Build two firmwares with addresses 192.168.1.32 and 192.168.1.40. $ od -Ax -t x8 | less 000000 00000712deadbeef 51000001c8c00008 000010 000000059af5ddb0 000e041000000010 000020 0000000000000000 000000000000c701 000030 0000c70100000000 0800800000000401 000040 0007000600058c8c 000b000a00090008 000050 000f000e000d000c 0013001200110010 000060 0017001600150014 001b001a00190018 000070 001f001e001d001c 0023002200210020 ....

MAC Address: : F:9C (Network Research) Nmap scan report for rfc1918.edu (192.168.2.57) Host is up (0.000074s latency).

Read 12340 words Wrote 12342 words to calling read Event (53)... Timeout (1000 milliseconds) occurred for UDP receive from target with URI: ipbusudp-2.0://192.168.1.001 Nmap scan report for rfc1918.edu (192.168.2.56) Host is up (0.000064s latency).

Rcms State Notifier - Unable to notify state change. Has find Rcms State Listener() been called at least once? [00000060] 08 00 09 00 0A 00 0B 00 0C 00 0D 00 0E 00 0F 00 ........ [00000070] 10 00 11 00 12 00 13 00 14 00 15 00 16 00 17 00 ........ [00000080] 18 00 19 00 1A 00 1B 00 1C 00 1D 00 1E 00 1F 00 ........ [00000090] 20 00 21 00 22 00 23 00 24 00 25 00 26 00 27 00 ........ [000000a0] 28 00 29 00 2A 00 2B 00 2C 00 2D 00 2E 00 2F 00 ........ [000000b0] 30 00 31 00 32 00 33 00 34 00 35 00 36 00 37 00 0.1.2.3. [000000c0] 38 00 39 00 3A 00 3B 00 3C 00 3D 00 3E 00 3F 00 8.9..... [000000d0] 40 00 41 00 42 00 43 00 44 00 45 00 46 00 47 00 .. Pick an action (h for menu): st *****AMC13 Status***** Status display detail level: 1 Control 0: 00320020 TTC Not Ready Control 1: 00000000 (All bits read 0x0) AMC Link Status: 00ffffff AMC13 Enabled Inputs: 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, 10, 11 AMC Input links locked: 00, 01, 02, 03, 04, 05, 06, 07 AMC Port Status: 00000036 AMC Link Versions incorrect: 01, 02, 04, 05 --All AMC Ports Synced-- AMC Bc0 Status: 0c62c231 Ports w/ Bc0 Locked: 01, 05, 06, 10, 11 EVB Counters: SDRAM Page No [000c]: 000c34ff Unread SDRAM Evts [000e]: 54834023 u HTR CRC Errors [000f]: 00340f7f (All 64-bit counters read 0x0) rd 0x20000 0x20 000000: 510000011f400008 CDF Header 000001: 1020000000016dc0 block header, n AMC=2 000002: 2e02000300010000 AMC1 info size=0x20003 2=first block e=EPV 000003: 2e02000300020000 AMC2 info size=0x20003 2=first block e=EPV 022002: 3ff73ff63ff53ff4 022004: 3ffb3ffa3ff93ff8 022006: 3fff3ffe3ffd3ffc Trailer is missing(?

[000000c0] 58 02 59 02 5A 02 5B 02 5C 02 5D 02 5E 02 5F 02 X. ls=3: Couldn't resolve host name' raised at get Value From EVM(/usr/local/src/xdaq/baseline12/trunk/daq/evb/src/common/bu/RUproxy.cc:539) .755 [139942756808448] WARN cms1.p: 33001.evb:: BU.instance(0). Please verify device selection, interface settings, target power and connections to the target device Severity: Error Component ID: 20100 Status Code: 13101 Module Name: TCF (TCF command: Device:start Session failed.) Unexpected JTAG ID 0x FFFFFFFE (expected 0x01edd03f).

[000000d0] 60 02 61 02 62 02 63 02 64 02 65 02 66 02 67 02 ..a.b.c. [000000e0] 68 02 69 02 6A 02 6B 02 6C 02 6D 02 6E 02 6F 02 h.i.j.k. [000000f0] 70 02 71 02 72 02 73 02 74 02 75 02 76 02 77 02 p.q.r.s. ]' raised at process(/usr/local/src/xdaq/baseline12/trunk/daq/pt/frl/src/common/Copy Worker.cc:583); originated by pt::frl::exception:: Exception 'Overflow of i2o: 32696' raised at process Copy(/usr/local/src/xdaq/baseline12/trunk/daq/pt/frl/src/common/Copy Worker.cc:301) Caught exception: exception:: Disk Writing 'Failed to get value from EVM at 33001/urn:xdaq-application:lid=12/event Count For Lumi Section? Note 1: Sending triggers does not successfully lead to building events to monitor buffer, Note 2: Bc0 locked only successfully locked if setup is done after complete power cycle of boards (physically removed from crate) read Repeat 0 0x1080 100000 terminate called after throwing an instance of 'uhal::exception:: Udp Timeout' what(): Timeout (1000 milliseconds) occurred for UDP receive from target with URI: ipbusudp-2.0://192.168.1.001 Using AMC13Tool found at /home/hazen/bin/AMC131: MMC: 2.2 IP: 192.168.1.62 192.168.1.63 vv: 0x0109 sv: 0x0021 sn: 96 temp: 732 2: MMC: 2.2 IP: 192.168.1.70 192.168.1.71 vv: 0x0109 sv: 0x0021 sn: 92 temp: 627 3: MMC: 2.2 IP: 192.168.1.126 192.168.1.127 vv: 0x0108 sv: 0x0021 sn: 64 temp: 761 4: MMC: 2.2 IP: 192.168.1.60 192.168.1.61 vv: 0x0109 sv: 0x0021 sn: 97 temp: 708 5: MMC: 2.2 IP: 192.168.1.54 192.168.1.55 vv: 0x0109 sv: 0x0021 sn: 100 temp: 595 6: MMC: 2.2 IP: 192.168.1.52 192.168.1.53 vv: 0x0109 sv: 0x0021 sn: 101 temp: 686 7: MMC: 2.2 IP: 192.168.1.72 192.168.1.73 vv: 0x1000 sv: 0x0020 sn: 91 temp: 386 8: MMC: 2.2 IP: 192.168.1.78 192.168.1.79 vv: 0x1000 sv: 0x0020 sn: 88 temp: 413 9: MMC: 2.2 IP: 192.168.1.76 192.168.1.77 vv: 0x1000 sv: 0x0020 sn: 89 temp: 370 10: MMC: 2.2 IP: 192.168.1.74 192.168.1.75 vv: 0x1000 sv: 0x0020 sn: 90 temp: 400 11: MMC: 2.2 IP: 192.168.1.106 192.168.1.107 vv: 0x0108 sv: 0x0021 sn: 74 temp: 706 12: MMC: 2.2 IP: 192.168.1.56 192.168.1.57 vv: 0x0109 sv: 0x0021 sn: 99 temp: 668 13: MMC: 2.2 IP: 192.168.1.90 192.168.1.91 vv: 0x0209 sv: 0x0021 sn: 82 temp: 702 Trying to fill the 2nd crate. Scan crate behaves badly (last couple of boards report 255's for IP addresses). From 128.197.254.113 icmp_seq=1 Time to live exceeded From 128.197.254.113 icmp_seq=2 Time to live exceeded From 128.197.254.113 icmp_seq=3 Time to live exceeded *****AMC13 Status***** Status display detail level: 1 Control 0: 56000009 DAQLSC Link Down Monitor Buffer Empty Control 1: 02070105 TTS out is TTC signal out Generate Internal L1A Run Mode AMC Link Status: 70000002 AMC13 Enabled Inputs: 01 --No AMC links locked-- AMC Port Status: 0fff0000 --All AMC Link Versions Correct-- Unsynced AMC Ports: 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, 10, 11 AMC Bc0 Status: 00000018 --No BC0s locked-- Local Trigger Control: 00000000 Periodic L1A every 0x1 orbit at BX = 500 0x1 trigger per burst EVB Counters: (All 32-bit counters read 0x0) Run time [0048]: 0000000b fe3aec10 Ready time [004a]: 0000000b fe3be392 Busy time [004c]: 00000000 00000001 L1A ovfl warn time [0050]: 00000000 00000001 AMC Counters: u HTR status and u HTR DTC status: ID[0] IP[192.168.115.8] Type: u HTR ID of u HTR (-1 for exiting the tool) :: [0] u HTR baseboard V1.0 Serial number 65535 Front Firmware revision : HF-4800 (41) 00.0c.00 Back Firmware revision : HF-4800 (41) 00.0e.10 Clock expected at 25.0000 MHz : 25.0000 MHz (front) 25.0000 MHz (back) Clock expected at 100.0000 MHz : 100.0000 MHz (front) 100.0000 MHz (back) Clock expected at 40.0800 MHz : 40.0004 MHz (front) 40.0004 MHz (back) Clock expected at 80.1600 MHz : 80.0008 MHz (front) 80.0008 MHz (back) Clock expected at 120.2400 MHz : 120.0012 MHz (front) 120.0012 MHz (back) Clock expected at 160.3200 MHz : 160.0016 MHz (front) 160.0016 MHz (back) Clock expected at 240.4800 MHz : 240.0024 MHz (front) 240.0024 MHz (back) Clock expected at 320.6400 MHz : 320.0031 MHz (front) 320.0032 MHz (back) Clock expected at 11.0000 k Hz : 11.2230 k Hz (front) 11.2240 k Hz (back) Clock expected at 0.1100 k Hz : 0.0000 k Hz (front) 0.0000 k Hz (back) Clock expected at 40.0800 MHz : 40.0004 MHz (front) 40.0004 MHz (back) Clock expected at 40.0800 MHz : 40.0004 MHz (front) 40.0004 MHz (back) Clock expected at 240.4800 MHz : 240.0024 MHz (front) 320.0032 MHz (back) STATUS Status summary of the u HTR card LINK Status and control of frontend links DTC TTC link and information received from AMC13/DTC CLOCK Clock module work SENSOR I2C sensors and controls TRIG Trigger-path work DAQ DAQ-path work TEST Functionality tests of u HTR Board FLASH Flash programming and readback menu LUMI LUMI-DAQ work EXIT Exit this tool status ================================================ Front FPGA: Back FPGA: Event Num : 5052417 5052417 Lumi Nibble : 0 0 Lumi Section : 0 0 CMS Run : 0 0 LHC Fill : 0 0 RATE_40MHz (MHz) : 40.00 40.00 RATE_ORBIT (k Hz) : 11.22 11.22 Bunch Count : 1225 2333 BC0 Error : 37034 58266 Single Error : 29428 56570 Double Error : 36388 36832 TTC Stream Phase : 0 0 TTC Stream Phase : Locked Locked Unable to enter programming mode. File 1:run000039_ls0001_index000001Ev N 000191 (000401) Bc N 5ea ID 0064 Evt_ty=1 [1 blocks, 0x9 words] Ev N 000192 (000402) Bc N 2b6 ID 0064 Evt_ty=1 [1 blocks, 0x9 words] Ev N 000193 (000403) Bc N 313 ID 0064 Evt_ty=1 [1 blocks, 0x9 words] Ev N 000194 (000404) Bc N 455 ID 0064 Evt_ty=1 [1 blocks, 0x9 words] Ev N 000195 (000405) Bc N 588 ID 0064 Evt_ty=1 [1 blocks, 0x9 words] Ev N 000196 (000406) Bc N 5f6 ID 0064 Evt_ty=1 [1 blocks, 0x9 words] Ev N 000001 (000001) Bc N 19c ID 0064 Evt_ty=1 [1 blocks, 0x9 words] Ev N 00c351 (050001) Bc N a5f ID 0064 Evt_ty=1 [1 blocks, 0x9 words] Ev N 0186a1 (100001) Bc N 5e2 ID 0064 Evt_ty=1 [1 blocks, 0x9 words] Ev N 0249f1 (150001) Bc N be8 ID 0064 Evt_ty=1 [1 blocks, 0x9 words] Ev N 030d41 (200001) Bc N 55c ID 0064 Evt_ty=1 [1 blocks, 0x9 words] Ev N 03d091 (250001) Bc N 5da ID 0064 Evt_ty=1 [1 blocks, 0x9 words] Slink_Express| SFP0| --|------------| BACKPRESSURE_TIME| 0x14D8BA436| BLOCKS| 0x 55BC8| BLOCKS_SENT| 0x 55BC8| EVENTS_SENT| 0x 55BC8| INITIALIZED| 1| LINKNOTFULL| 0| LINK_UP| 1| NO_BACKPRESSURE| 1| PACKETS_RCVD| 0x 55BE2| PACKETS_SENT| 0x 8131E2| REVISION| 0x 5E100001| SFP_LSC_DOWN| 0| TEST_MODE| 0| WORDS| 0x 303A08| WORDS_SENT| 0x 303A08| State_Timers| COUNT| PERCENT| --|------------|--------| BUSY| 0x 100001| | L1A_IN_OFW| 3| | OVERFLOW_WARNING| 0x 497B9E52| | READY| 0x82F6C3C36| 100| RUN| 0x878F7DA7F| | T2_TTC| BCNTERR| --|--------| VALUE| 1| TTC_Rx| ENC| RAW| --|----------|----------| STATE| RDY (0x0)| RDY (0x8)| Fixing issues with the 10G FEROL software on CMS3, should help with cms2. Disconnect local Ethernet cable on cmssun1 from local switch, move to direct connection to Vadatech MCH. # # demo BGO # # enable AMC13 (needed to start TTC output) en 1 f t # channel 0, short command 0x1c # every 1000 orbits, repeating # bgo 0 short 0xc repeat # # now set up the history filter to exclude BC0 # ttc f s 0 0x01 0xfe ttc f on # # clear the history and enable # ttc h clr ttc h on # sleep 0.5 # # display the history, last 10 entries # ttc h d Able to send events from SN85 to the FEROL with fake data enabled and a rate of ~10k Hz with the local o 1 1 setting. Next trying the same thing but with 258 producing fake events. 000770 deadbeef 0000001a 1d500008 51000012 000780 008a7470 00000000 00000010 00170410 000790 00000000 00000000 0000c00c 00000000 0007a0 00000000 0000c00b 00000412 bbee8000 0007b0 001761d5 00284511 ffff2000 12080000 0007c0 45110012 2000bbee 000061d7 20004539 0007d0 0000ffff 00001208 ad8c0000 a000000d 0007e0 deadbeef 0000001a 1d500008 51000013 0007f0 008a7530 00000000 00000010 00170410 000800 00000000 00000000 0000c00c 00000000 000810 00000000 0000c00c 00000413 1bee8000 000820 001761d5 00284511 ffff2000 13080000 000830 00000a13 1bee8000 001761d5 00284511 000840 ffff2000 13080000 766b0000 a000000d Working on AMC13 "pre-ship" certification test. Meanwhile, trying to program the thing in Wu's test fixture.

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The word count in the AMC13 header (see below) is 0b instead of 0c, with a zero fill word added (correctly) by the AMC13. This should be taken care of by the u TCA backplane, no? We need to remove these ICs one by one to find the culprit. The ICs are U9, U16, U19 and U13 Caps are C146, C147, C148, C161, C162, C186, C187 and C159 show_fru FRU Information: ---------------- FRU Device State Name ========================================== 0 MCH M4 NMCH-CM 3 mcmc1 M4 NAT-MCH-MCMC 12 AMC8 M4 BU AMC13 40 CU1 M4 VT VT095 41 CU2 M4 VT VT095 50 PM1 M4 VT UTC010 ========================================== nat show_sensorinfo 12 Sensor Information for AMC 8 ======================================================== # SDRType Sensor Entity Inst Value State Name -------------------------------------------------------- 0 MDev Loc 0xc1 0x68 BU AMC13 0 Full 0xf2 0xc1 0x68 0x01 Hotswap 1 Full Temp 0xc1 0x68 27.00 ok T2 Temp 2 Full Voltage 0xc1 0x68 12.54 ok 12V 3 Full Voltage 0xc1 0x68 3.315 ok 3.3V 4 Full Voltage 0xc1 0x68 1.2000 ok 1.2V 5 Full 0x08 0xc1 0x68 0x00 0x02 Pwr Good 6 Full 0x15 0xc1 0x68 0x00 0x01 Alarm Level 7 Full 0xc0 0xc1 0x68 0x00 0x2d FPGA Config -------------------------------------------------------- FRU Information: ---------------- FRU Device State Name ========================================== 0 MCH M4 NMCH-CM 3 mcmc1 M4 NAT-MCH-MCMC 9 AMC5 M4 BU AMC13 40 CU1 M4 VT VT095 41 CU2 M4 VT VT095 51 PM2 M4 VT UTC010 ========================================== nat show_sensorinfo 9 Sensor Information for AMC 5 ================================================================== # SDRType Sensor Entity Inst Value State Name ------------------------------------------------------------------ 0 MDev Loc 0xc1 0x65 BU AMC13 0 Full 0xf2 0xc1 0x65 0x01 Hotswap 1 Full Temp 0xc1 0x65 26.00 ok T2 Temp 2 Full Voltage 0xc1 0x65 12.48 ok 12V 3 Full Voltage 0xc1 0x65 3.315 ok 3.3V 4 Full Voltage 0xc1 0x65 1.2000 ok 1.2V 5 Full 0x08 0xc1 0x65 0x00 0x02 Pwr Good 6 Full 0x15 0xc1 0x65 0x00 0x01 Alarm Level 7 Full 0xc0 0xc1 0x65 0x00 0x2d FPGA Config ------------------------------------------------------------------ $ cd hcal/hcal UHTR $ ./bin/linux/x86_64_slc5/u 192.168.115.8 (0) IP[192.168.115.8] Type: UHTR ID of u HTR (-1 for exiting the tool) :: Front Firmware revision : (00) Back Firmware revision : (00) Clock expected at 25.0000 MHz : 25.0000 MHz (front) 25.0000 MHz (back) Clock expected at 100.0000 MHz : 100.0000 MHz (front) 100.0000 MHz (back) Clock expected at 40.0800 MHz : 39.9999 MHz (front) 39.9999 MHz (back) Clock expected at 80.1600 MHz : 79.9998 MHz (front) 79.9998 MHz (back) Clock expected at 120.2400 MHz : 119.9997 MHz (front) 119.9997 MHz (back) Clock expected at 160.3200 MHz : 159.9997 MHz (front) 159.9997 MHz (back) Clock expected at 240.4800 MHz : 239.9995 MHz (front) 239.9995 MHz (back) Clock expected at 320.6400 MHz : 319.9994 MHz (front) 319.9993 MHz (back) Clock expected at 11.0000 k Hz : 11.2230 k Hz (front) 11.2230 k Hz (back) Clock expected at 0.1100 k Hz : 0.0000 k Hz (front) 0.0000 k Hz (back) Clock expected at 40.0800 MHz : 39.9999 MHz (front) 39.9999 MHz (back) Clock expected at 40.0800 MHz : 39.9999 MHz (front) 39.9999 MHz (back) Clock expected at 240.4800 MHz : 0.0000 MHz (front) 56.7837 MHz (back) STATUS Status summary of the u HTR card LINK Status and control of frontend links DTC Information received from DTC CLOCK Clock module work SENSOR I2C sensors and controls TRIG Trigger-path work DAQ DAQ-path work TEST Functionality tests of u HTR Board FLASH Flash programming and readback menu LUMI LUMI-DAQ work EXIT Exit this tool ctl DAQ F2B Links 0 : Status = f Errors = 19349 (0.000000e 00 Hz) Words = 8675 (0.000000e 00 Hz) 1 : Status = f Errors = 19349 (0.000000e 00 Hz) Words = 8675 (0.000000e 00 Hz) 2 : Status = f Errors = 19349 (0.000000e 00 Hz) Words = 9424 (0.000000e 00 Hz) DAQ Path : ENABLED ZS(per sample) Last EVN: 10 Or N : 2983852 Header Occupancy : 0 (Peak : 1) Samples: 10 Presamples : 4 Pipeline Length : 50 ZS Mask (one means ignore) : 0x 0 TP Samples: 14 TP Presamples : 11 TP ZS : TP_NZS Module Id : 0 (0x0) BC Offset : 0 (1) Set Module Id (2) Set BC Offset (3) Set NSAMPLES (4) Set PRESAMPLES (5) Set Pipeline Length (6) Set ZS Mask (7) Enable DAQ Path (toggle) (8) Reset DAQ Path (9) Toggle NZS (10) Toggle Mark-And-Pass ZS (11) Toggle ZS Sum-By-Two (12) Dump ZS Thresholds (13) Edit ZS Thresholds (14) Uniform ZS (15) Set TP PRESAMPLES (16) Set TP SAMPLES (17) Toggle ZS for TP (18) Toggle SOI-only for TP ( Anything else will just return to the original menu ) Selection : [-1] 3 New nsamples : [10] 10 DAQ F2B Links 0 : Status = f Errors = 19349 (0.000000e 00 Hz) Words = 8675 (0.000000e 00 Hz) 1 : Status = f Errors = 19349 (0.000000e 00 Hz) Words = 8675 (0.000000e 00 Hz) 2 : Status = f Errors = 19349 (0.000000e 00 Hz) Words = 9424 (0.000000e 00 Hz) DAQ Path : ENABLED ZS(per sample) Last EVN: 10 Or N : 3737623 Header Occupancy : 0 (Peak : 1) Samples: 10 Presamples : 4 Pipeline Length : 50 ZS Mask (one means ignore) : 0x 0 TP Samples: 14 TP Presamples : 11 TP ZS : TP_NZS Module Id : 0 (0x0) BC Offset : 0 (1) Set Module Id (2) Set BC Offset (3) Set NSAMPLES (4) Set PRESAMPLES (5) Set Pipeline Length (6) Set ZS Mask (7) Enable DAQ Path (toggle) (8) Reset DAQ Path (9) Toggle NZS (10) Toggle Mark-And-Pass ZS (11) Toggle ZS Sum-By-Two (12) Dump ZS Thresholds (13) Edit ZS Thresholds (14) Uniform ZS (15) Set TP PRESAMPLES (16) Set TP SAMPLES (17) Toggle ZS for TP (18) Toggle SOI-only for TP ( Anything else will just return to the original menu ) Selection : [-1] 4 New presamples : [4] 4 DAQ F2B Links 0 : Status = f Errors = 19349 (0.000000e 00 Hz) Words = 8675 (0.000000e 00 Hz) 1 : Status = f Errors = 19349 (0.000000e 00 Hz) Words = 8675 (0.000000e 00 Hz) 2 : Status = f Errors = 19349 (0.000000e 00 Hz) Words = 9424 (0.000000e 00 Hz) DAQ Path : ENABLED ZS(per sample) Last EVN: 10 Or N : 3803540 Header Occupancy : 0 (Peak : 1) Samples: 10 Presamples : 4 Pipeline Length : 50 ZS Mask (one means ignore) : 0x 0 TP Samples: 14 TP Presamples : 11 TP ZS : TP_NZS Module Id : 0 (0x0) BC Offset : 0 (1) Set Module Id (2) Set BC Offset (3) Set NSAMPLES (4) Set PRESAMPLES (5) Set Pipeline Length (6) Set ZS Mask (7) Enable DAQ Path (toggle) (8) Reset DAQ Path (9) Toggle NZS (10) Toggle Mark-And-Pass ZS (11) Toggle ZS Sum-By-Two (12) Dump ZS Thresholds (13) Edit ZS Thresholds (14) Uniform ZS (15) Set TP PRESAMPLES (16) Set TP SAMPLES (17) Toggle ZS for TP (18) Toggle SOI-only for TP ( Anything else will just return to the original menu ) Selection : [-1] 5 New pipeline length : [50] 50 DAQ F2B Links 0 : Status = f Errors = 19349 (0.000000e 00 Hz) Words = 8675 (0.000000e 00 Hz) 1 : Status = f Errors = 19349 (0.000000e 00 Hz) Words = 8675 (0.000000e 00 Hz) 2 : Status = f Errors = 19349 (0.000000e 00 Hz) Words = 9424 (0.000000e 00 Hz) DAQ Path : ENABLED ZS(per sample) Last EVN: 10 Or N : 3842107 Header Occupancy : 0 (Peak : 1) Samples: 10 Presamples : 4 Pipeline Length : 50 ZS Mask (one means ignore) : 0x 0 TP Samples: 14 TP Presamples : 11 TP ZS : TP_NZS Module Id : 0 (0x0) BC Offset : 0 (1) Set Module Id (2) Set BC Offset (3) Set NSAMPLES (4) Set PRESAMPLES (5) Set Pipeline Length (6) Set ZS Mask (7) Enable DAQ Path (toggle) (8) Reset DAQ Path (9) Toggle NZS (10) Toggle Mark-And-Pass ZS (11) Toggle ZS Sum-By-Two (12) Dump ZS Thresholds (13) Edit ZS Thresholds (14) Uniform ZS (15) Set TP PRESAMPLES (16) Set TP SAMPLES (17) Toggle ZS for TP (18) Toggle SOI-only for TP ( Anything else will just return to the original menu ) Selection : [-1] 8 DAQ F2B Links 0 : Status = f Errors = 19349 (0.000000e 00 Hz) Words = 8675 (0.000000e 00 Hz) 1 : Status = f Errors = 19349 (0.000000e 00 Hz) Words = 8675 (0.000000e 00 Hz) 2 : Status = f Errors = 19349 (0.000000e 00 Hz) Words = 9424 (0.000000e 00 Hz) DAQ Path : ENABLED ZS(per sample) Last EVN: 0 Or N : 39 Header Occupancy : 0 (Peak : 0) Samples: 10 Presamples : 4 Pipeline Length : 50 ZS Mask (one means ignore) : 0x 0 TP Samples: 14 TP Presamples : 11 TP ZS : TP_NZS Module Id : 0 (0x0) BC Offset : 0 (1) Set Module Id (2) Set BC Offset (3) Set NSAMPLES (4) Set PRESAMPLES (5) Set Pipeline Length (6) Set ZS Mask (7) Enable DAQ Path (toggle) (8) Reset DAQ Path (9) Toggle NZS (10) Toggle Mark-And-Pass ZS (11) Toggle ZS Sum-By-Two (12) Dump ZS Thresholds (13) Edit ZS Thresholds (14) Uniform ZS (15) Set TP PRESAMPLES (16) Set TP SAMPLES (17) Toggle ZS for TP (18) Toggle SOI-only for TP ( Anything else will just return to the original menu ) Selection : [-1] 7 $ cd source ~/(to set the environment) $ cd ~/TTS_ctrl $ ./periodic_120hz Orbit Length: -o 3563 BX Trigger Delay: -d 500 BX Orbit Count: -n 0 orbits Trigger Spacing: -s 25 BX Triggers per orbit: -t 1 triggers Repeat period: -r 100 orbits Random threshold: -p 0 / 65535 TTS latency -l 0 BXn (0 sec) TTS sample mask -m 0 TTC cmd BCN -w 1000 Allow L1A in gap -g 0 Trigger rule 1: not enabled Trigger rule 2: not enabled Trigger rule 3: not enabled Trigger rule 4: not enabled Rule enable mask: 0x0 $ cd ../ttc $ -x setup_revision Load TTCvi_base = 0xf10000 Load vme_slot = 0x13 Load log_level = error Load hal_path = /home/daqowner/dist/hal/hcal/ Load vme_bus = caen:0 Load ttc_bus = caen:0 HAL search path set to /opt/xdaq/hal/hcal/ Overriding default HAL path with /home/daqowner/dist/hal/hcal/ from PROGRAMMER_HAL_PATH Looking for HAL addresstable files in directory /home/daqowner/dist/hal/hcal/ (change by setting PROGRAMMER_HAL_PATH environment variable) INFO: Logger set up V2718 firmware : 2.00 A2818 firmware : 0.06 VMELib Release : 2.30.2 INFO: bus Adapter set up INFO: DCC constructed DCC1 created INFO: DCC connected INFO: TTCvi set up - dcc-setup HAL() (/home/daqowner/dist/hal/hcal/DCC_LRB.dat,/home/daqowner/dist/hal/hcal/DCC_LTB.dat,/home/daqowner/dist/hal/hcal/DCC_log12.dat,/home/daqowner/dist/hal/hcal/DCC_log123_conf.dat,/home/daqowner/dist/hal/hcal/DCC_logicboardv4_2DCC::initialize()... DCC::get Master Device() DCC revision is 2c36 [Script setup_start] # # DCC script to setup TTCvi # ttc/write 0x82 0xf000 # reset BGO fifos ttc/write 0x80 0xff64 # enable external orbit, disable triggers ttc/write 0x92 10 # inhibit 0 delay (250ns) ttc/write 0x94 10 # inhibit 0 duration (250ns) ttc/write BData0 0x00800000 # write one word (BCR, cmd=01) to fifo 0 ttc/write 0x90 0xd # enable BG0 channel 0 ttc/cmd 2 # send ECR ttc/cmd 0x28 # send OCR ttc/trig 4 # disable L1A TTC L1A source set to 4 (VME) q $ No triggers are sent, and the TTCvi panel has LEDs lit which I have never seen lit before, namely "L1A Req" (a yellow light) and "Req0" (a red light..one may have been lit before and I may just not have noticed). The LED lighting didn't have anything to do with the problem, apparently. by first writting Spartan v6 to flash at 0x000000 (its old location) as if programming the Header, power cycling the AMC13 module with the NAT tool, reprogramming the flash Header (0x000000), Golden (0x100000), Spartan (0x200000), and Virtex (0x400000), and then issuing the software command to reconfigure from flash.